
2003 Microchip Technology Inc.
DS30569B-page 75
PIC16F870/871
TABLE 9-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
FIGURE 9-11:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
R0IF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
0000 -000
18h
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
1Ah
RCREG
USART Receive Register
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
—
CCP1IE
TMR2IE
TMR1IE
0000 -000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000
Legend:
x
= unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master reception.
Note
1:
Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.
CREN bit
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
'0'
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
'0'
Q1 Q2 Q3 Q4